 Functional verification培训 |
| 入学要求 |
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学员学习本课程应具备下列基础知识：
◆ 电路系统的基本概念。 |
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班级规模及环境 |
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为了保证培训效果，增加互动环节，我们坚持小班授课，每期报名人数限5人，多余人员安排到下一期进行。 |
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上课时间和地点 |
上课地点：【上海】：同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】：电影大厦(地铁一号线大剧院站)/深圳大学成教院
【北京分部】：北京中山学院/福鑫大楼 【南京分部】：金港大厦(和燕路) 【武汉分部】：佳源大厦（高新二路）
【成都分部】：领馆区1号（中和大道）
最近开课时间(周末班/连续班/晚班）：Functional verification培训：即将开课，具体请咨询客服 |
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学时 |
◆课时： 一个月
◆外地学员：代理安排食宿（需提前预定）
☆合格学员免费颁发相关资格证书，提升您的职业资质
作为最早专注于嵌入式培训的专业机构，曙海嵌入式学院提供的证书得到本行业的广泛认
可，学员的能力得到大家的认同。
☆合格学员免费推荐工作
★实验设备请点击这儿查看★ |
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最新优惠 |
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◆团体报名优惠措施：两人95折优惠，三人或三人以上9折优惠 。注意：在读学生凭学生证，即使一个人也优惠500元。 |
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质量保障 |
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1、培训过程中，如有部分内容理解不透或消化不好，可免费在以后培训班中重听；
2、培训结束后,培训老师留给学员手机和Email,免费提供半年的技术支持，充分保证培训后出效果；
3、培训合格学员可享受免费推荐就业机会。 ☆合格学员免费颁发相关工程师等资格证书，提升您的职业资质。专注高端培训13年，曙海提供的证书得到本行业的广泛认可，学员的能力得到大家的认同，受到用人单位的广泛赞誉。 |
Functional verification培训
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第一阶段 Incisive Comprehensive Coverage
Course Description
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course explores Incisive? comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of SystemC, VHDL, Verilog?, and mixed-language designs. Not all coverage features are available with all languages.
The course discusses the collection and analysis of the following types of coverage:
- Code (block, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog covergroups
- Control-oriented functional coverage using PSL and SystemVerilog assertions
Learning Objectives
After completing this course you will be able to:
- Effectively use the Incisive comprehensive coverage with your SystemC, VHDL, Verilog, and mixed-language designs
第二阶段 Incisive SystemC, VHDL, and Verilog Simulation
Course Description
This course addresses Incisive? mixed-language (SystemC?, VHDL, and Verilog?) event-driven digital simulation. The course takes you through the compilation, elaboration, simulation, and interactive debug process, at each step explaining the most commonly used options. This course treats the SystemC, VHDL, and Verilog languages equivalently. You can do the labs in your choice of language.
Learning Objectives
After completing this course you will be able to:
- Compile, elaborate, link, and simulate a design: Understand how to specify the inputs and outputs at each phase, configure the design, and control each process for effectiveness and optimal performance.
- Debug a design with the textual interactive simulation interface: Briefly examine most of the interactive commands for the purpose of understanding what capabilities are available and how you can use them in a script to drive batched regression tests; practice these capabilities in the context of a scripted debug scenario.
- Debug a design with the graphical interactive simulation interface: Examine many of the capabilities of the feature-rich SimVision graphical simulation analysis environment; practice these capabilities in the context of a scripted debug scenario.
- Utilize some of the other tools available to assist your simulation-related efforts to: Verify your platform's patch level, protect your intellectual property, “lint” your design and filter and sort the analysis report, manage your library of compiled design objects, compare simulation traces, package your design for transmittal, and much more.
- Optionally: Understand the issues involved with mixed-language instantiation, simulation, and debugging; examine the mechanics of interconnecting components of multiple languages; choose and simulate a mixed-language design configuration containing at least one HDL component and at least one SystemC component.
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